Efficient Implementation of DVI Protocol on FPGA

Document Type : Special Issue

Authors

• Sara Ershadi-Nasab ¹
• Danial Bayati ¹
• Saeed Yazdani ²

¹ Computer Engineering department, Ferdowsi University of Mashhad.

² Computer Engineering department, Ferdowsi university of Mashhad.

10.22067/cke.2025.91345.1142

Abstract

This paper presents a general-purpose hardware implementation of the digital visual interface (DVI) protocol on the Xilinx Virtex-6 ML605 FPGA platform for real-time display of digital processing results. The design enables direct output of processed data from the FPGA to an external monitor without relying on external processors or software-based rendering tools. It addresses key challenges in timing synchronization, pixel formatting, and interfacing with the onboard Chrontel CH7301C encoder to support resolutions up to 1920×1080 at 60 Hz. A lightweight processing pipeline is developed in Verilog to convert multidimensional outputs into a sequential stream of pixel data conforming to the DVI protocol. As a case study, a lightweight convolutional neural network trained on the CIFAR-10 dataset is implemented on the FPGA, and its classification probabilities are displayed as a probability map on an LCD. Experimental results confirm low resource utilization and real-time performance, validating the system’s applicability in embedded applications such as machine learning inference, image processing, and real- time monitoring. This work demonstrates the feasibility of FPGA- based platforms for efficiently displaying digital video output in intelligent edge systems.

Keywords

• Digital visual interface
• field programmable gate array
• image processing
• real-time
• video processing
• Xilinx Virtex-6

Main Subjects

• Computer Architecture

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References

1. Park and D. Kim. (2024, Jan.). Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review. IEEE Access. [Online]. 12, pp. 22880–22891. Available: https://doi.org/10.1109/ACCESS.2024.3359037
2. Singh, A. S. Mandal, C. Shekhar, and A. Vohra. (2017, Jun.). Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform. Journal of imaging. [Online]. 3(2), p. 20. Available: https://doi.org/10.3390/jimaging3020020.
3. Plusquellic, E. E. Tsiropoulou, and C. Minwalla. (2023). Privacy-Preserving Authentication Protocols for IoT Devices Using FPGA and DVI Integration. IEEE Transactions on Emerging Topics in Computing. [Online]. Available: https://ece-research.unm.edu/jimp/pubs/SiRF_Authentication_FINAL.pdf
4. Park and S. Kim. (2023). Overviewing AI-Dedicated Hardware for On-Device AI in Smartphones. In Artificial Intelligence and Hardware Accelerators. Springer International Publishing. [Online]. pp. 127–150. Available: https://doi.org/10.1007/978-3-031-22170-5_4
5. Jain, S. Giraldo, J. De Roose, L. Mei, B. Boons, and M. Verhelst. (2023, Aug.). TinyVers: A Tiny Versatile System-on-Chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE Journal of Solid-State Circuits. [Online]. 58(8), pp. 2360–2371. Available: https://doi.org/10.1109/JSSC.2023.3236566
6. Peddie. (2023). The GPU Environment—Hardware. In The History of the GPU—Eras and Environment. Springer International Publishing. [Online]. pp. 151–200. Available: https://doi.org/10.1007/978-3-031-13581-1_5
7. G. Bailey, “Design for Embedded Image Processing on FPGAs,” John Wiley & Sons, 2023.
8. Chrontel, Inc. (2014). CH7301C DVI Transmitter Device Datasheet, Rev. 2.1. [Online]. Available: CH7301C DVI Transmitter Device.
9. A. Nuño-Maganda, J. H. Jiménez-Arteaga, J. H. Barron-Zambrano, Y. Hernández-Mier, J. C. Elizondo-Leal, A. Díaz-Manríquez, C. Torres-Huitzil, and S. Polanco-Martagón. (2022). Implementation and Integration of Image Processing Blocks in a Real-Time Bottle Classification System. Scientific Reports. [Online]. 12(1), p. 4868. Available: https://doi.org/10.1038/s41598-022-08777-x
10. Baisi, “A Machine Learning Approach to Optimizing CNN Deployment on Tile-Based Systems-on-Chip,” Doctoral dissertation, Politecnico di Torino, 2024.
11. Kyrkou, C. Ttofis, and T. Theocharides. (2011, Sep.). FPGA-Accelerated Object Detection Using Edge Information. In 2011 21st International Conference on Field Programmable Logic and Application, pp. 167–170. [Online]. Available: https://doi.org/10.1109/FPL.2011.38
12. Abernot, “Digital Oscillatory Neural Network Implementation on FPGA for Edge Artificial Intelligence Applications and Learning,” Doctoral dissertation, Université de Montpellier, 2023.
13. Guarrera, “Real-time processing of neuronal network activity measured by a high-density microelectrode matrix through an FPGA card,” Thesis, Univ. of Padova, 2022.
14. Kong, F. Yu, W. Yao, S. Cai, J. Zhang, and H. Lin. (2024). Memristor-Induced Hyperchaos, Multiscroll and Extreme Multistability in Fractional-Order HNN: Image Encryption and FPGA Implementation. Neural Networks. [Online]. 171, pp. 85–103. Available: https://doi.org/10.1016/j.neunet.2023.12.008
15. W. Park, H. Lee, B. Kim, D. G. Kang, S. O. Jin, H. Kim, and H. J. Lee. (2019, Jan.). A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. [Online]. 28(1), pp. 101–114. Available: https://doi.org/10.1109/TVLSI.2019.2936260
16. Wang and Z. Luo. (2022, Oct.). A Review of the Optimal Design of Neural Networks Based on FPGA. Applied Sciences. [Online]. 12(21), p. 10771. Available: https://doi.org/10.3390/app122110771
17. Liu and Y. Chen. (2023). Hybrid FPGA-GPU Co-Design for Real-Time Neural Network Inference and Visualization. In IEEE 13th Symposium on Computer Applications & Industrial Electronics (ISCAIE), pp. 712–718. [Online]. Available: https://doi.org/10.1109/ISCAIE57739.2023.10165432
18. Thyagarajan et al. (2023). Video Analytics with FPGA-Based Smart Cameras for Object Recognition in Hockey Games. Presented at International Conference on Networking and Communications (ICNWC). [Online]. Available: https://doi.org/10.1109/ICNWC57852.2023.10127549
19. Nowosielski, R. Przesmycki, and M. Nowosielski. (2016, Aug.). Compromising Emanations from VGA and DVI Interface. Presented at 2016 Progress in Electromagnetic Research Symposium (PIERS), pp. 1024–1028. [Online]. Available: https://doi.org/10.1109/PIERS.2016.7734570
20. T. Hoang, N. H. Nguyen, and X. T. Nguyen. (2012). A Real-Time Object-Recognition System Based on PCNN Algorithm. International Journal of Neural computing [Online]. Available: https://thuchoang90.github.io/assets/pp/2012_ICDV.pdf
21. Fang, Z. Mei, A. Shrestha, Z. Zhao, Y. Li, and Q. Qiu. (2020, Nov.). Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs. In Proceedings of the 39th international conference on computer-aided design, pp. 1–9. [Online]. Available: https://doi.org/10.1145/3400302.3415608
22. Farabet, B. Martini, P. Akselrod, S. Talay, Y. LeCun, and E. Culurciello. (2010, May). Hardware Accelerated Convolutional Neural Networks for Synthetic Vision Systems. In Proceedings of 2010 IEEE international symposium on circuits and systems, pp. 257–260. [Online]. Available: https://doi.org/10.1109/ISCAS.2010.5537908
23. Yildiz, E. Cesur, K. Kayaer, V. Tavsanoglu, and M. Alpay. (2014, Oct.). Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator. IEEE Transactions on Circuits and Systems I: Regular Papers. [Online]. 62(1), pp. 130–138. Available: https://doi.org/10.1109/TCSI.2014.2345502
24. Kayaer and V. Tavsanoglu. (2009, Apr.). A New Cellular Neural Network Emulator Architecture Processing Video Real-Time. In 2009 IEEE 17th Signal Processing and Communications Applications Conference, pp. 1024–1028. [Online]. Available: https://doi.org/10.1109/SIU.2009.5136446
25. Abernot, “Digital Oscillatory Neural Network Implementation on FPGA for Edge Artificial Intelligence Applications and Learning,” Ph.D. dissertation, Univ. of Montpellier, 2023.
26. L. Savkay, N. Yildiz, E. Cesur, M. E. Yalcin, and V. Tavsanoglu. (2013, Sep.). Realization of Preprocessing Blocks of CNN Based CASA System on FPGA. In 2013 European Conference on Circuit Theory and Design (ECCTD), pp. 1–4. [Online]. Available: https://doi.org/10.1109/ECCTD.2013.6662238
27. Antonik, Application of FPGA to Real-Time Machine Learning: Hardware Reservoir Computers and Software Image Processing. Springer, 2018.
28. Ahilan and E. A. K. James. (2011, Dec.). Design and Implementation of Real-Time Car Theft Detection in FPGA. In Third International Conference on Advanced Computing, pp. 353–358. [Online]. Available: https://doi.org/10.1109/ICoAC.2011.6165201
29. Davutoglu, N. Yildiz, U. E. Ayten, and V. Tavsanoglu. (2018). Real-Time Frame Buffer Implementation Based on External Memory Using FPGA. Procedia Computer Science. [Online]. 131, pp. 641–646. Available: https://doi.org/10.1016/j.procs.2018.04.307
30. Fasih, C. Schwarzlmueller, K. Kyamakya, and F. A. Machot. (2010). Video Enhancement for ADAS Systems Based on FPGA and CNN Platform. International Journal of Signal & Image Processing. [Online]. 1(3).
31. Padhi and S. V. (2020). Image-Classification-Using-CNN-on-FPGA. [Online].