Two Efficient Ternary Adder Designs Based On CNFET Technology

Document Type : Original Article

Authors

1 Computer engineering department, Amirkabir university of technology, Gramsar campus, Garmsar, Iran

2 Computer engineering department, Amirkabir university of technology, Garmsar campus, Garmsar, Iran

Abstract

Full adder is one of the essential circuits among the various processing elements used in VLSI and other technologies circuits, because they are mainly employed in other arithmetic circuits, such as multi-digit adders, subtractors, and multipliers. This paper proposes two efficient ternary full adders based on Carbon Nanotube Field-Effect Transistor (CNFET) technology. Using the adjustable nanotube diameter in CNFETs, these adders utilize arbitrary threshold voltages so that arithmetic operations can be performed with a radix of 3. For performance analysis, the proposed adder circuits are simulated in HSPICE with 32nm CNFET technology. In these simulations, different inputs are applied at different frequencies with different load capacitances placed at the output. Simulation results have shown that the proposed adders not only improve the speed, power consumption, and Power Delay Product (PDP) of the existing state-of-the-art designs but also improve the design complexity by reducing the number of transistors contained within the circuit.

Keywords

Main Subjects


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